module minors(  input [15:0]data1,
                input [15:0]data2,
                input isNeg1,
                input isNeg2,
                input [2:0]enable,
                input done,
                input reset,
                input sysclk,
                output reg [15:0]result,
                output reg isNeg,
                output reg suc);


parameter init=2'b00,start=2'b01,finish=2'b10;
reg [1:0]state;
reg [1:0]nstate;

initial begin
        nstate <= init;
end

always @(posedge sysclk) begin
        state = nstate;
end


always @(posedge sysclk) begin
        if (reset) begin
                result = 16'h0;
                isNeg = 1'b0;
                suc = 1'b0;
                nstate = init;
        end
        else begin
                case(state)
                        init:   begin
                                if (enable==3'b010) begin
                                        result = 16'h0;
                                        isNeg = 1'b0;
                                        suc = 1'b0;
                                        nstate = start;
                                        end
                                else begin
											nstate = init;
											suc=1'b0;
											end
                                end
                        start:  begin
                                if (isNeg1^isNeg2) begin
					if (isNeg1) begin isNeg = 1'b1; result = data1 + data2; end
					else begin isNeg = 1'b0; result = data1 + data2; end
					end
                                else begin
					if(isNeg1==1'b0) begin
							 if (data1 >= data2) begin isNeg = 1'b0; result = data1 - data2; end
							 else begin isNeg = 1'b1; result = data2 - data1; end
							 end
					else begin
							if (data1 >= data2) begin isNeg = 1'b1; result = data1 - data2; end
							else begin isNeg = 1'b0; result = data1 - data2; end
						end
				end
                                suc = 1'b1;
                                nstate = finish;
                                end
                        finish: begin
                                if (done) begin
                                        suc = 1'b0;
                                        nstate = init;
                                        end
                                else nstate = finish;
                                end
                endcase
        end
end

endmodule
